Advanced Hardware Design for Error Correcting Codes

Advanced Hardware Design for Error Correcting Codes

Paperback(Softcover reprint of the original 1st ed. 2015)

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Overview

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering.

• Examines how to optimize the architecture of hardware design for error correcting codes;

• Presents error correction codes from theory to optimized architecture for the current and the next generation standards;

• Provides coverage of industrial user needs advanced error correcting techniques.

Advanced Hardware Design for Error Correcting Codesincludes a foreword by Claude Berrou.

Product Details

ISBN-13: 9783319355108
Publisher: Springer International Publishing
Publication date: 08/23/2016
Edition description: Softcover reprint of the original 1st ed. 2015
Pages: 192
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

About the Author

Cyrille Chavet is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France. Philippe Coussy is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France.

Table of Contents

User Needs.- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding.- Implementation of Polar Decoders.- Parallel architectures for Turbo Product Codes Decoding.- VLSI implementations of sphere detectors.- Stochastic Decoders for LDPC Codes.- MP-SoC/NoC architectures for error correction.- ASIP design for multi-standard channel decoders.- Hardware design of parallel interleaver architecture: a survey.

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