Testing Static Random Access Memories: Defects, Fault Models and Test Patterns

Testing Static Random Access Memories: Defects, Fault Models and Test Patterns

by Said Hamdioui

Paperback(Softcover reprint of the original 1st ed. 2004)

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Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed.
-Fault primitive based analysis of memory faults,
-A complete framework of and classification memory faults,
-A systematic way to develop optimal and high quality memory test algorithms,
-A systematic way to develop test patterns for any multi-port SRAM,
-Challenges and trends in embedded memory testing.

Product Details

ISBN-13: 9781441954305
Publisher: Springer US
Publication date: 12/09/2010
Series: Frontiers in Electronic Testing , #26
Edition description: Softcover reprint of the original 1st ed. 2004
Pages: 221
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

Preface. Acknowledgements. Symbols and notations.
I: Introductory. 1. Introduction. 1.1. Test philosophy. 1.2. Memory technology. 1.3. Modeling amd testing faults in SRAMs. 2. Semiconductor memory architecture. 2.1. Memory models. 2.2. External memory behavior. 2.3. Functional memory behavior. 2.4. Electrical memory behavior. 2.5. Memory process technology. 3. Space of memory faults. 3.1. Concept of fault primitive. 3.2. Classification of fault primitives. 3.3. Single-port faults. 3.4. Two-port fault primitives. 4. Preparation for circuit simulation. 4.1. Selected multi-port SRAM cell. 4.2. Modeling of spot defects. 4.3. Definition and location of opens. 4.4. Definition and location of shorts. 4.5. Definition and location of bridges. 4.6. Simulation model. 4.7. Simulation methodology. 4.8. Simulation results for the fault free case.
II: Testing single-port and two-port SRAMs. 5. Experimental analysis of two-port SRAMs. 5.1. The to-be simulated spot defects. 5.2. Simulation results. 5.3. Realistic fault models. 5.4. Fault probability analysis. 6. Tests for single-port and two-port SRAMs. 6.1. Notation for march tests. 6.2. Tests for single-port faults. 6.3. Conditions for detecting two-port faults. 6.4. Tests for two-port faults. 6.5. Comparison with other tests. 6.6. Test strategy. 6.7. Test results versus fault probabilities. 7.7.1. Classification of two-port memories. 7.2. Realistic faults for 2P memories. 7.3. Tests for restricted two-port memories. 7.4. Test strategy for restricted two-port memories.
III: Testing p-port SRAMs. 8. Experimental analysis of p-port SRAMs. 8.1. The to-be simulated spot defects. 8.2. Simulation results. 8.3. Realistic fault models for three-port memories. 8.4. Fault probabilities analysis. 8.5. Realistic fault models for p-port memories. 9. Tests for p-port SRAMs. 9.1. Conditions for detecting p-port faults. 9.2. Tests for p-port faults. 9.3. Test strategy. 10. Testing restricted p-port SRAMs. 10.1. Classification of p-port memories. 10.2.Realistic faults for restricted p-port memories. 10.3. Tests for restricted p-port memories. 10.4. Test strategy for restricted p-port memories. 11. Trends in embedded memory testing. 11.1. Introduction. 11.2. Fault modeling. 11.3. Test algorithm design. 11.4. Built-in-self test (BIST). 11.5. Built-in-self repair (BISR). 11.6. Putting all together. Bibliography.
A: Simulation results for two-port SRAMs. A.1. Simulation results for opens. A.2. Simulation results for shorts. A.3. Simulation results for bridges.
B: Simulation results for three-port SRAMs. B.1. Simulation results for opens and shorts. B.2. Simulation results for bridges.

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